![]() Port H is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. ![]() Port pins can provide internal pull-up resistors (selected for each bit). Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port F serves as analog inputs to the A/D Converter. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. ![]() As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Port B has better driving capabilities than the other ports. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The following figure is ATMEGA2560-16AU Pinout.
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